产品中心 RDC IAD（互联网接入设备）100系列是一系列低功耗32位微处理器内核，专为在互联网接入中用作x86兼容应用而构建。IAD 100HV包括R3306，R3306包含CPU、GPU、DDR2控制器、NB、PCI、快速以太网、SPI和南桥C6036。
SB C6036包含高清音频（HDA）、IDE、低引脚数（LPC）控制器和其他外围设备。为了提供最佳性能，RDC SB C6036必须配备带NB的RDC CPU。得益于RDC功率优化的处理器架构，RDC IAD100系列为价格合理的消费电子设备提供了优势，从而提高了成本效益和延长了电池寿命。节省的系统电源时间将允许更多的操作。操作系统兼容性包括WinCE、Linux、Windows XP、Windows Embedded XP、VxWorks OS。这种新的双芯片平台是无风扇计算系统的创意，有助于推动快速出现的具有x86兼容性的绿色和纤薄应用类别。
适合无风扇设计应用
低耗电表现
轻薄体积外型
提供完整量产设计参考
可降低整体负担成本
产品应用
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Features
● x86-Compatible Processor Core – 6-stage pipeline ● Floating point unit support – Extends CPU instruction set to include Trigonometric, Logarithmic and Exponential – Implements ANSI/IEEE standard 754-1985 for binary Floating-Point Architecture ● Embedded I / D Separated L1 Cache – 16K I-Cache, 16K D-Cache – Supports 4 way set associative cache architecture – Snooping mechanism support for data coherence between main memory and cache ● Embedded L2 Cache – 4-way 256KB L2 Cache – Write through or write back policy ● System DDRII Control Interface – 16 bits data bus – DDRII clock support up to 333MHz – DDRII size support up to 512M ● GPU Control Unit – GPU DDRII Control Interface – VGA controller – 2D Graphics engine support ● MAC Controller x 1 – Supports one-port 10/100 Fast Ethernet MAC – IEEE 802.3u MII interface – IEEE 802.3x flow control in full-duplex mode – Descriptor architecture for packet TX/RX ● PCI Control Interface – Up to 3 sets PCI master device – 3.3V I / O ● SPI Interface x2 – Supports two SPI interfaces. – One for boot up function from SPI flash ● External SPI Interface ● JTAG Interface supported for S.W. debugging ● IDE Controller – Supports 2 channels Ultra-DMA 100 ( Disk x 4 ) – Primary channel support SD card ● LPC ( Low Pin Count ) Bus Interface ● PCI Control Interface – 3.3V I / O ● HDA Controller ● DMA Controller ● Interrupt Controller ● Counter / Timers – 2 sets of 8254 timer controller | – Timer output is 5V tolerance I/O on 2nd Timer ● Real Time Clock – Less than 5uA (3.0V) power comsuption in Internal RTC Mode while chip is power-off. ● FIFO UART Port x 3 ( 3 sets COM Port ) – Compatible with 16C550 / 16C552 – Default internal pull-up – Supports the programmable baud rate generator with the data rate from 50 to 460.8K bps – The character options are programmable for 1 start bits; 1, 1.5 or 2 stop bits; even, odd or no parity; 5~8 data bits – Supports TXD_En Signal – Port 80h output data could be sent to COM1 by software programming ● Parallel Port x 1 – Supports SPP/EPP/ECP mode ● General Programmable I/O – Supports 40 programmable I / O pins – Each GPIO pin can be individually configured to be an input/output pin – GPIO_P0 and GPIO_P1 with interrupt support (input/output) ● USB 2.0 Host Support – Supports HS, FS and LS – 4 ports ● USB 1.1 Device Support – 1 port – Supports FS with 3 programmable endpoint ● Speaker out ● I2C bus x 2 – Compliant w/t V2.1 – Some master code (general call, START and CBUS) not support. ● Input clock – 14.318 MHz – 32.768 KHz ● Output clock – 24 MHz – 25 MHz ● Operating Voltage Range – I / O voltage: 1.8V ± 5% , 3.3 V ± 10 % ● Operating temperature – 0℃ ~ 70℃ ● Package Type - 19x19mm, 441-Ball LFBGA |
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